1. Field
Example embodiments relate to a semiconductor memory device, and for example, to a multi bit flash memory device and/or a method of programming the same.
2. Description of Related Art
Semiconductor memory devices are largely classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices have faster reading and writing speeds, but stored contents of the volatile semiconductor memory devices disappear if no external power is applied. On the other hand, the non-volatile semiconductor memory devices retain stored contents even if there is no power supply. Therefore, the non-volatile semiconductor memory devices are used to store contents, which must remain regardless of power supply. Examples of the non-volatile semiconductor memory devices are a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Because erase and write operations are relatively difficult in the MROM, PROM, and EPROM, common users may not be able to update memory contents. However, because erase and write operations may be electrically done in the EEPROM, the EEPROM is more widely used in system programming or auxiliary memory devices, which require continuous updating. A flash EEPROM has a higher degree of integration compared to a typical EEPROM, and the flash EEPROM may be more advantageous for a high-capacity auxiliary memory device. Among the flash EEPROM, a NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory) has a remarkably higher degree of integration, compared to other flash EEPROMs.
Recently, as the demand for a higher degree of integration in a memory device increases, multi bit memory devices that store multi bit data in one memory cell are used.
If 1-bit data is stored in each memory cell, each memory cell has one of two threshold voltage distributions, one of which corresponds to data 1 or data 0. On the other hand, if 2-bit data is stored in each memory cell, each memory cell has one of four threshold voltage distributions. If 3-bit data is stored in each memory cell, each memory cell has one of eight threshold voltage distributions. Recently, various technologies for storing 4-bit data in one memory cell are under active development.
FIG. 1 is a view of conventional processes of programming multi bit data by a page unit according to a binary ordering method. To store 4-bit data in one memory cell, the 4-bit data is programmed by a page unit. After programming a first page Page 1, memory cells respectively have a threshold voltage state corresponding to 1 or 0. After programming a second page Page 2, the memory cells respectively have a threshold voltage state corresponding to 11, 01, 10, and 00. After programming a third page Page 3, the memory cells respectively have a threshold voltage state corresponding to 111, 011, 101, 001, 110, 010, 100, and 000. A verify operation performed after programming a fourth page Page 4 (or, an MSB page) includes a preliminary read operation and a verify read operation. In the preliminary read operation, first read voltages 10 are provided to a word line of the selected memory cells. In the verify read operation, second read voltages 20 are applied to the word line of selected memory cells. After applying a program voltage, if a threshold voltage of a cell, whose MSB page is 0, is determined to exist between a first read voltage VpreX and a second read voltage VfyX, the memory cell is determined as a verify pass. The memory cells determined as verify pass become program inhibit in a program loop.
FIG. 2 is an example timing diagram of a program operation according to the sequence in FIG. 1. Referring to FIG. 2, after a program execution operation, a preliminary read operation Pre RD sensing a threshold voltage state, and a verify read operation Verify are respectively performed on all threshold voltage states. A second loop for reprogramming is performed on cells, which are determined as fail during a first loop. In each loop, preliminary read pre RD and verify read Verify operations are performed as in the first loop. The preliminary read pre RD and verify read Verify operations repeat until all the selected memory cells become pass.
FIG. 3 is a view of conventional processes of programming multi bit data by a page unit according to a gray ordering method. After programming a first page Page 1, each memory cell has a threshold voltage state corresponding to 1 or 0. After programming a second page Page 2, each memory cell has a threshold voltage state corresponding to 11, 10, 00, and 01. After programming a third page Page 3, each memory cell has a threshold voltage state corresponding to 111, 110, 100, 101, 001, 000, 010, and 011. A preliminary read operation is performed by first read voltages 30 to read program states up to the three pages, in order to perform a program operation on a fourth page Page 4 (or, an MSB page). According to the result of the preliminary read operation, cells where data of the fourth page to be programmed is 1, become program inhibit. According to the program inhibit, cells, where data of the fourth page Page 4 is 1, maintain a threshold voltage state at the time if the third page Page 3 is programmed. Among the cells selected by the preliminary read operation, cells, where data of the fourth page Page 4 to be programmed is 0, are programmed with a threshold voltage corresponding to 0. After applying a program voltage (e.g., an ISPP voltage) to the selected memory cells once, a verify read operation that determines if the memory cells are programmed or not is performed by second read voltages 40. The memory cells determined as verify pass through the verify read operation become program inhibit, and the memory cells determined as fail are set to be reprogrammed.
FIG. 4 is an example timing diagram of a program operation according to the sequence in FIG. 3. Referring to FIG. 4, before programming a fourth page Page 4, a preliminary read Pre RD operation is performed on the program result of the previous third page Page 3. The memory cells selected by the preliminary read operation are programmed to a target threshold voltage state by applying a program voltage Vpgm to a word line during a program execution interval. A verify operation is performed during a verify interval in order to determine if each memory cell is programmed or not. During the verify interval, the threshold voltage state of each memory cell is read by second read voltages Vfy1 to Vfy8. A second program loop for reprogramming is performed on the cells that are determined as fail in the first program loop. The second program loop is performed on the cells that are determined as fail by the verify read operation. The program execution operation and verify operation repeat until all the selected memory cells become pass.
According to the above description with reference to the drawings, program executions of a fourth page Page 4 (or, an MSB page) are simultaneously performed on the all the selected memory cells. The selected memory cells have a same level of program voltage during the program execution. In the above programming method, at least four latches in a page buffer are required to perform a preliminary read operation, and a time for programming multi bit data increases.